standard logic cell

基本解釋

Standard logic cells, memory design and IO cell design.
標(biāo)準(zhǔn)邏輯單元，存儲(chǔ)電路設(shè)計(jì)及輸入輸出單元設(shè)計(jì)。
The decomposition of multilevel logic functions based on standard cell libraries used in ASIC synthesis is presented in the paper.
本文提出在ASIC綜合技術(shù)中基于標(biāo)準(zhǔn)單元庫(kù)的多級(jí)邏輯函數(shù)分解技術(shù)。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
此門陣列采用的BFL預(yù)功能級(jí)標(biāo)準(zhǔn)邏輯單元，具有九種組合邏輯功能及兩種不同選擇的驅(qū)動(dòng)能力，并具有輸出電平調(diào)節(jié)功能。